Apparatus and methods including source gates

ABSTRACT

Apparatus and methods are disclosed, such as an apparatus that includes a string of charge storage devices associated with a pillar (e.g., of semiconductor material), a source gate device, and a source select device coupled between the source gate device and the string. Additional apparatus and methods are described.

PRIORITY APPLICATION

This application is a continuation of U.S. application Ser. No. 17/027,425, filed Sep. 21, 2020, which is a continuation of U.S. application Ser. No. 16/237,337, filed Dec. 31, 2018, which is a continuation of U.S. application Ser. No. 15/721,007, filed Sep. 29, 2017, which is a continuation of U.S. application Ser. No. 15/166,029, filed May 26, 2016, which is a continuation of U.S. application Ser. No. 14/451,145, filed Aug. 4, 2014, which is a continuation of U.S. application Ser. No. 13/210,194, filed Aug. 15, 2011, now issued as U.S. Pat. No. 8,797,806, all of which are incorporated herein by reference in their entirety.

BACKGROUND

Semiconductor memory devices are used in many electronic devices such as personal digital assistants (PDAs), laptop computers, mobile phones and digital cameras. Some of these semiconductor memory devices have arrays of charge storage transistors.

BRIEF DESCRIPTION OF THE DRAWINGS

Some embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings in which:

FIGS. 1A and 1B are electrical schematic diagrams of a block of memory cells according to various embodiments of the invention;

FIG. 2 is a top view of a semiconductor construction according to various embodiments of the invention;

FIG. 3 is a cross-sectional view of a semiconductor construction according to various embodiments of the invention;

FIG. 4 is a cross-sectional view of a semiconductor construction according to various embodiments of the invention;

FIG. 5 is a top view of a semiconductor construction according to various embodiments of the invention;

FIG. 6 is a cross-sectional view of a semiconductor construction according to various embodiments of the invention;

FIG. 7 is a cross-sectional view of a semiconductor construction according to various embodiments of the invention;

FIG. 8 is a cross-sectional view of a semiconductor construction according to various embodiments of the invention;

FIG. 9 is a flow diagram of a method according to various embodiments of the invention; and

FIG. 10 is a diagram illustrating a system according to various embodiments of the invention.

DETAILED DESCRIPTION

An array of charge storage devices according to various embodiments of the invention may function as an array of memory cells in a memory device such as a NOT AND (NAND) memory device.

For the purposes of this document, a “tier of semiconductor material” can mean semiconductor material formed in a same plane, rank, row, or unit, such as in a horizontal or vertical or sloped plane, row, rank or unit of a structure. Meanwhile, an “apparatus” can refer to circuitry, devices or systems.

FIGS. 1A and 1B are electrical schematic diagrams of a block 100 of memory cells according to various embodiments of the invention. The block 100 includes strings 110 of charge storage devices 118. A single NAND memory device may include multiple strings.

The strings 110 are arranged in rows and columns in the block 100. FIG. 1A shows a single row of four strings 110 aligned with one vertical plane of the block 100 of memory cells. FIG. 1B shows three rows each having four strings 110 (for a total of twelve strings 110). Each string 110 includes four charge storage devices 118 coupled serially, although each string 110 may include fewer or more charge storage devices 118. Each string 110 includes a source select device 122 at a bottom of the string 110 and a drain select device 126 at a top of the string 110.

The drain select device 126 is coupled between the charge storage devices 118 and a data line 130. There are four data lines 130 that are coupled to the strings 110, each data line 130 being coupled to three of the strings 110 in a column of the block 100. The source select device 122 is coupled between the charge storage devices 118 and a source gate 140.

The source select device 122 has a source select gate (SGS) coupled to a SGS line 150. There are three SGS lines 150 that are coupled to the source select devices 122 in the block 100, each SGS line 150 being coupled to gates of four of the source select devices 122 in a row of the block 100. The SGS lines 150 are substantially orthogonal to the data lines 130.

The drain select device 126 has a drain select gate (SGD) coupled to a SGD line 160. There are three SGD lines 160 that are coupled to the drain select devices 126 in the block 100, each SGD line 160 being coupled to gates of four of the drain select devices 126 in a row of the block 100. The SGD lines 160 are substantially orthogonal to the data lines 130. The source gate 140 substantially controls conduction in a first channel in the string 110 represented by a first source gate device 170 and a second channel in a substrate (not shown) represented by a second source gate device 172. The source gates 140 of all of the strings 110 in the block 100 are coupled to a single source gate line 176. The second source gate devices 172 in each row of the block 100 are coupled in series between the respective strings 110 and a common source line 180.

Each of the charge storage devices 118 may comprise a transistor having a charge trap or a floating gate, for example. Each charge storage device 118 may comprise a multi-state device capable of holding multiple separate and distinct threshold voltage states (e.g., corresponding to respective ranges of threshold voltages), each threshold voltage state representing different data. Each of the source select device 122 and the drain select device 126 may comprise a transistor.

FIG. 2 is a top view of a semiconductor construction 200 according to various embodiments of the invention. The semiconductor construction 200 includes three-hundred and sixty pillars 204 comprising a semiconductor material. For example, the pillars 204 may comprise polysilicon. Each of the pillars 204 provides a channel for multiple charge storage devices in a string in a NAND memory device.

The pillars 204 are arranged into eight rows of forty five columns with each pillar 204 occupying an intersection of a row and a column. The pillars 204 are divided into five blocks 210, 212, 214, 216 and 218 separated from each other by either empty space 220 or a conductive member (e.g., a conductive slot) 224 coupled to an n+ type diffusion region 228. The empty space 220 and space around the members 224 are filled with a dielectric (not shown) such as, for example, silicon dioxide (SiO₂). Each of the blocks 210, 212, 214, 216 and 218 includes seventy two of the pillars 204 in eight rows of nine columns. The pillars 204 in each row across all of the blocks 210, 212, 214, 216 and 218 are coupled together by a data line 232 or 233 that may be used to sense a state of one of the charge storage devices in the row. The data lines 232 and 233 may comprise, for example, polysilicon or metal, including one or more of cobalt (Co), titanium (Ti), tungsten (W), nickel (Ni) or tantalum (Ta) according to various embodiments of the invention. The semiconductor construction 200 can include different numbers of pillars 204 arranged in different numbers of rows and columns in different numbers of blocks according to various embodiments of the invention.

FIG. 3 is a cross-sectional view of the semiconductor construction 200 along line 3-3 according to various embodiments of the invention and FIG. 4 is a cross-sectional view of the semiconductor construction 200 along line 4-4 according to various embodiments of the invention. FIG. 3 illustrates the pillars 204 in blocks 210 and 212 and one of the members 224 between the blocks 210 and 212. FIG. 4 illustrates the pillars 204 in the block 216.

The pillars 204 extend from the data lines 232 and 233 to a p-type silicon well 310. The silicon well 310 is formed in an n-type silicon well 312 which is formed in a p-type silicon substrate 316. The n+ type diffusion region 228 is formed in the silicon well 310 and can reduce resistance to current flow in the silicon well 310. A number of tiers of metal or semiconductor material surround or partially surround the pillars 204 between the data lines 232 and 233 and the silicon well 310 in each of the blocks 210, 212, 214, 216 and 218. The tiers are separated from each other by a dielectric (not shown) such as, for example, silicon dioxide (SiO₂). A majority of the tiers are access lines 320 and 322 to control the charge storage devices that receive and release charge through the pillars 204. Each of the access lines 320 and 322 surrounds or partially surrounds all of the pillars 204 in a block such as the blocks 210 and 212 shown in FIG. 3.

A tier between the access lines 320 and 322 and the data lines 232 and 233 is divided into drain select gates (SGDs) 330 and 360 that may substantially control conduction between the pillars 204 and the data lines 232 and 233. The eight pillars 204 in each column are surrounded or partially surrounded by a separate SGD 330 or 360. A tier below the access lines 320 and 322 is divided into source select gates (SGSs) 340 and 370 that may at least partially control conduction between the pillars 204 and the silicon well 310. The eight pillars 204 in each column are surrounded or partially surrounded by a separate SGS 340 or 370.

A tier between the SGSs 340 and 370 and the silicon well 310 comprises a source gate 350. In the embodiment depicted in FIGS. 2-4, source gate 350 surrounds or partially surrounds all of the pillars 204 in a block such as the block 210 or the block 212 shown in FIG. 3. The source gate 350 may at least partially control conduction between the pillars 204 and the silicon well 310.

The members 224 each comprise a conductive structure, such as one having a wall shape, coupled to the n+ type diffusion region 228 in the silicon well 310, and that projects from the substrate 316. The members 224 comprise, for example, a semiconductor such as polysilicon or a metal such as tungsten. Each member 224 and the n+ type diffusion region 228 coupled to the member 224 can be used as a common source line in the semiconductor construction 200. The members 224 can be used to bias the silicon well 310 to a potential as desired. The members 224 can also reduce the resistance to current flow in the silicon well 310.

The access lines 320 and 322, the SGDs 330 and 360, the SGSs 340 and 370 and the source gate 350 can be separated from each other by a dielectric such as, for example, silicon dioxide (SiO₂). The access lines 320 and 322, the SGDs 330 and 360, the SGSs 340 and 370 and the source gate 350 may comprise tiers of a semiconductor material such as silicon or polysilicon or polysilicon doped with Phosphorous or Boron. The access lines 320 and 322, the SGDs 330 and 360, the SGSs 340 and 370 and the source gate 350 may also comprise metal including one or more of Cobalt (Co), Titanium (Ti), Tungsten (W), Nickel (Ni) or Tantalum (Ta) according to various embodiments of the invention.

The access lines 320 and 322 control charge storage devices surrounding or partially surrounding each pillar 204. Each charge storage device may comprise, for example, a floating gate transistor or a charge trap transistor. The SGDs 330 and 360, the SGSs 340 and 370 and the source gate 350 control transistors surrounding or partially surrounding each pillar 204.

Operations involving charge storage devices in the semiconductor construction 200 will be described with reference to a selected charge storage device having a channel in a selected pillar 204 between the SGD 360 and the SGS 370 in the block 212. The selected pillar 204 is coupled to the data line 233. The selected charge storage device is controlled by the access line 322.

The selected charge storage device is read when the voltages shown in Table 1 are applied to the semiconductor construction 200.

TABLE 1 Block 212 Block 210 Data line 233 ~0.3 V ~0.3 V Data lines 232 ~0 V   ~0 V Access line 322 0 to ~3 V   ~0 V Access lines 320 ~6 V   ~0 V SGD 360 ~4 V N/A SGDs 330 ~0 V   ~0 V SGS 370 ~4 V N/A SGSs 340 ~0 V   ~0 V Source gate 350 ~5 V   ~0 V Member 224 ~0 V   ~0 V Silicon Well 310 ~0 V   ~0 V

Approximately 4 volts is applied to turn on the SGD 360 and the SGS 370 and approximately 5 volts is applied to turn on the source gate 350 in the block 212 to couple the selected pillar 204 to the data line 233 and the silicon well 310. A channel develops in the silicon well 310 under the block 212 due to the potential of the source gate 350 to carry charge from the block 212 to the member 224 and the n+ type diffusion region 228 coupled to the member 224 that can be a common source line. The access line 322 in the block 212 is coupled to between approximately 0 volts and approximately 3 volts in stages to gradually turn on the selected charge storage device, which can be in one of a plurality of charge storage states. Approximately 6 volts are applied to the other access lines 320 in the block 212 to render the other charge storage devices associated with the selected pillar 204 conductive. The other SGDs 330 and SGSs 340 in the block 212 are coupled to approximately 0 volts and are not conductive, such that the channel does not receive charge from the pillars 204 other than the selected pillar 204. The data line 233 is precharged to approximately 0.3 volts to allow the selected charge storage device to be read, and the other data lines 232 are at approximately 0 volts. The access lines 320, the SGDs 330, the SGSs 340 and the source gate 350 in the block 210 are at approximately 0 volts. The data lines 232 and 233 and the silicon well 310 are at the same potential for the blocks 210 and 212.

Charge storage devices associated with pillars other than the selected pillar 204 can be influenced during a read by the access lines 320 at approximately 6 volts, and may be programmed unintentionally. This unintentional programming is called read disturb. The inventors have discovered that the challenge noted above, as well as others, can be addressed by turning on the source gate 350 at 5 volts to allow the SGSs 340 of the pillars other than the selected pillar 204 to be turned off to substantially electrically isolate the pillars other than the selected pillar 204 from the silicon well 310. The SGSs 340 that are not conductive substantially prevent conduction between the pillars other than the selected pillar 204 and the silicon well 310 to substantially prevent read disturb activity with respect to those pillars 204.

The selected charge storage device is programmed when the voltages shown in Table 2 are applied to the semiconductor construction 200.

TABLE 2 Block 212 Block 210 Data line 233 0 to ~1 V 0 to ~1 V Data lines 232 ~2.3 V ~2.3 V Access line 322 ~20 V ~0 V Access lines 320 ~10 V ~0 V SGD 360 ~3 V N/A SGDs 330 ~0 V ~0 V SGS 370 0 to ~3 V N/A SGSs 340 0 to ~3 V ~0 V Source gate 350 ~0 V ~0 V Member 224 0 to ~2 V 0 to ~2 V Silicon Well 310 ~0 V ~0 V

Approximately 3 volts is applied to turn on the SGD 360. The SGSs 340 and 370 in the block 212 are biased to between approximately 0 and approximately 3 volts and the member 224 is biased to between approximately 0 and approximately 2 volts. The SGDs 330 and the source gate 350 in the block 212 and the silicon well 310 are biased to approximately 0 volts. Approximately 20 volts are applied to the access line 322 in the block 212 to turn on the selected charge storage device to program it. Approximately 10 volts are applied to the other access lines 320 in the block 212 to render the other charge storage devices associated with the selected pillar 204 conductive. The SGDs 330 that are biased to approximately 0 volts are not conductive such that the pillars in the block 212 other than the selected pillar 204 are floating and have a potential that rises to approximately 8 volts due to the potential on the access lines 320 of approximately 10 volts to substantially prevent programming. The data line 233 coupled to the selected pillar 204 is between approximately 0 and approximately 1 volt to allow the selected charge storage device to be programmed and the other data lines 232 are biased to approximately 2.3 volts. The access lines 320, the SGDs 330, the SGSs 340 and the source gate 350 in the block 210 are at approximately 0 volts. The data lines 232 and 233 and the silicon well 310 are at the same potential for the blocks 210 and 212.

The source gate 350 is switched off to substantially reduce leakage of current to the n+ type diffusion region 228 and the member 224 and this can reduce program disturb activity during programming operations. The voltage applied to the SGSs 340 and 370 can be higher than the approximately 3 volts to reduce an electromagnetic field between the SGSs 340 and 370 and the access lines 320 and 322.

The selected charge storage device is erased when the voltages shown in Table 3 are applied to the semiconductor construction 200.

TABLE 3 Block 212 Block 210 Data lines 232, 233 ~20 V ~20 V Access lines 320, 322  ~0 V ~20 V SGDs 330, 360 ~20 V ~20 V SGSs 340, 370 ~20 V ~20 V Source gate 350 ~20 V ~20 V Member 224 ~20 V ~20 V Silicon Well 310 ~20 V ~20 V

Approximately 20 volts is applied to the silicon well 310 such that the potential on the pillars 204 rises to approximately 20 volts. The SGSs 340 and 370, the member 224, the source gate 350, the SGDs 330 and 360 and the data lines 232 and 233 are left floating and rise to approximately 20 volts from capacitive coupling with the pillars 204. Approximately 0 volts are applied to the access lines 320 and 322 in the block 212 to erase the charge storage devices associated with the pillar 204 above the SGS 370. The access lines 320 in the block 210 are also left floating and rise to approximately 20 volts from capacitive coupling with the pillars 204.

FIG. 5 is a top view of a semiconductor construction 500 according to various embodiments of the invention. The semiconductor construction 500 includes two-hundred and fifty-six pillars 504 comprising a semiconductor material. For example, the pillars 504 may comprise polysilicon. Each of the pillars 504 provides a channel for multiple charge storage devices in a string in a NAND memory device.

The pillars 504 are divided into four blocks 510, 512, 514 and 516 separated from each other by a conductive member 524 coupled to an n+ type diffusion region 528. Each of the blocks 510, 512, 514 and 516 includes 64 of the pillars 504 separated into sub-blocks 529, each sub-block 529 including 16 of the pillars 504. Each sub-block 529 is separated from neighboring sub-blocks 529 in the same block by an n+ type diffusion region 530. Sixteen data lines 532 and 533 are coupled to tops of the pillars 504, and the pillars 504 are arranged in two staggered columns in each sub-block 529. The columns of the pillars 504 are substantially perpendicular to the data lines 532 and 533 such that each data line 532 and 533 is coupled to a top of only one of the pillars 504 in each sub-block 529 of the semiconductor construction 500. Each data line 532 and 533 may be used to sense a state of one of the charge storage devices in one of the sub-blocks 529. The data lines 532 and 533 may comprise, for example, polysilicon or metal, including one or more of cobalt (Co), titanium (Ti), tungsten (W), nickel (Ni) or tantalum (Ta), according to various embodiments of the invention.

FIG. 6 is a cross-sectional view of the semiconductor construction 500 along line 6-6 according to various embodiments of the invention and FIG. 7 is a cross-sectional view of the semiconductor construction 500 along line 7-7 according to various embodiments of the invention. FIG. 6 shows the pillars 504 in the blocks 510 and 512 and one of the members 524 between the blocks 510 and 512. Half of the pillars 504 in the blocks 510 and 512 are shown in cross-section and half of the pillars 504 in the blocks 510 and 512 are not shown in cross-section but are staggered and behind the pillars 504 shown in cross-section. The pillars 504 that are staggered and behind the pillars 504 shown in cross-section are coupled to a data line 532 behind the data line 533 shown in FIG. 6. FIG. 7 shows eight of the pillars 504 and half of the data lines 532 and 533 in block 514 for purposes of brevity and clarity.

The pillars 504 extend from the data lines 532 and 533 to a p-type silicon well 610. The silicon well 610 is formed in an n-type silicon well 612 which is formed in a p-type silicon substrate 616. The n+ type diffusion regions 528 and 530 are formed in the silicon well 610 and can reduce resistance to current flow in the silicon well 610. A number of tiers of metal or semiconductor material surround or partially surround the pillars 504 between the data lines 532 and 533 and the silicon well 610 in each of the blocks 510, 512, 514 and 516. The tiers are separated from each other by a dielectric (not shown) such as, for example, silicon dioxide (SiO₂). A majority of the tiers comprise access lines 620 and 622 to control the charge storage devices that receive and release charge through the pillars 504. All of the pillars 504 in a sub-block 529 are surrounded or partially surrounded by respective access lines 620 or 622.

A tier between the access lines 620 and 622 and the data lines 532 and 533 is divided into SGDs 630 and 660 that may substantially control conduction between the pillars 504 and the data lines 532 and 533. The pillars 504 in each sub-block 529 are surrounded or partially surrounded by a separate SGD 630 or 660. A tier below the access lines 620 and 622 is divided into SGSs 640 and 670 that may at least partially control conduction between the pillars 504 and the silicon well 610. The pillars 504 in each sub-block 529 are surrounded or partially surrounded by a separate SGS 640 or 670. A tier between the SGSs 640 and 670 and the silicon well 610 is a source gate 650. The pillars 504 in each sub-block 529 are surrounded or partially surrounded by a separate source gate 650. The source gates 650 may also at least partially control conduction between the pillars 504 and the silicon well 610.

The members 524 each comprise a conductive structure, such as one having a wall shape, coupled to the n+ type diffusion region 528 in the silicon well 610, and that projects from the substrate 616. The members 524 comprise, for example, a semiconductor such as polysilicon or a metal such as tungsten. Each member 524 and the n+ type diffusion region 528 coupled to the member 524 can be used as a common source line in the semiconductor construction 500. The members 524 can be used to bias the silicon well 610 to a potential as desired. The members 524 can also reduce the resistance to current flow in the silicon well 610.

The access lines 620 and 622, the SGDs 630 and 660, the SGSs 640 and 670 and the source gate 650 can be separated from each other by a dielectric such as, for example, silicon dioxide (SiO₂). The access lines 620 and 622, the SGDs 630 and 660, the SGSs 640 and 670 and the source gate 650 may comprise tiers of a semiconductor material such as silicon or polysilicon or polysilicon doped with Phosphorous or Boron. The access lines 620 and 622, the SGDs 630 and 660, the SGSs 640 and 670 and the source gate 650 may also comprise metal including one or more of cobalt (Co), titanium (Ti), tungsten (W), nickel (Ni) or tantalum (Ta) according to various embodiments of the invention. The access lines 620 and 622 control charge storage devices associated with each pillar 504. The SGDs 630 and 660, the SGSs 640 and 670 and the source gate 650 control transistors surrounding or partially surrounding each pillar 504. Each charge storage device may comprise, for example, a floating gate transistor or a charge trap transistor.

Operations involving charge storage devices in the semiconductor construction 500 will be described with reference to a selected charge storage device having a channel in a selected pillar 504 between the SGD 660 and the SGS 670 in the block 512. The selected pillar 504 is coupled to the data line 533. The selected charge storage device is controlled by the access line 622.

The selected charge storage device is read when the voltages shown in Table 4 are applied to the semiconductor construction 500.

TABLE 4 Block 512 Block 510 Data line 533 ~0.3 V ~0.3 V Data lines 532 ~0 V   ~0 V Access line 622 0 to ~3 V   ~0 V Access lines 620 ~6 V   ~0 V SGD 660 ~4 V   ~0 V SGDs 630 ~0 V   ~0 V SGS 670 ~4 V   ~0 V SGSs 640 ~0 V   ~0 V Source gate 650 ~5 V   ~0 V Member 524 ~0 V   ~0 V Silicon Well 610 ~0 V   ~0 V

Approximately 4 volts is applied to turn on the SGD 660 and the SGS 670 and approximately 5 volts is applied to turn on the source gates 650 in the block 512 to couple the selected pillar 504 to the data line 533 and the silicon well 610. A channel develops in the silicon well 610 under the block 512 due to the potential of the source gate 650 to carry charge from the block 512 to the member 524 and the n+ type diffusion region 528 coupled to the member 524 that can be a common source line. The access line 622 in the block 512 is biased to a potential from approximately 0 to approximately 3 volts in stages to gradually turn on the selected charge storage device, which can be in one of a plurality of charge storage states. Approximately 6 volts are applied to the other access lines 620 in the block 512 and render the other charge storage devices associated with the selected pillar 504 conductive. The other SGDs 630 and SGSs 640 in the block 512 are biased to approximately 0 volts and are not conductive such that the channel does not receive charge from the pillars 504 other than the selected pillar 504. The data line 533 is precharged to approximately 0.3 volts to allow the selected charge storage device to be read, and the other data lines 532 are at approximately 0 volts. The access lines 620, the SGDs 630, the SGSs 640 and the source gate 650 in the block 510 are at approximately 0 volts. The data lines 532 and 533 and the silicon well 610 are at the same potential for the blocks 510 and 512. The pillar 504 that is between the SGD 660 and the SGS 670 that is not selected is not selected because it's coupled to one of the data lines 532 at approximately 0V.

The source gates 650 in the block 512 are turned on at 5 volts to allow the SGSs 640 of the pillars other than the selected pillar 504 to be turned off to substantially electrically isolate the pillars other than the selected pillar 504 from the silicon well 610. The SGSs 640 that are not conductive substantially prevent conduction between the pillars other than the selected pillar 504 and the silicon well 610 to substantially prevent read disturb in those pillars.

The selected charge storage device is programmed when the voltages shown in Table 5 are applied to the semiconductor construction 500.

TABLE 5 Block 512 Block 510 Data line 533 0 to ~1 V 0 to ~1 V Data lines 532 ~2.3 V ~2.3 V Access line 622 ~20 V ~0 V Access lines 620 ~10 V ~0 V SGD 660 ~3 V N/A SGDs 630 ~0 V ~0 V SGS 670 0 to ~3 V N/A SGSs 640 0 to ~3 V ~0 V Source gate 650 ~0 V ~0 V Member 524 0 to ~2 V 0 to ~2 V Silicon Well 610 ~0 V ~0 V

Approximately 3 volts is applied to turn on the SGD 660 in the block 512. The SGSs 640 and 670 in the block 512 are biased to between approximately 0 and approximately 3 volts and the member 524 is biased to between 0 and approximately 2 volts. The SGDs 630 and the source gate 650 in the block 512 and the silicon well 610 are biased to approximately 0 volts. Approximately 20 volts are applied to the access line 622 in the block 512 to turn on the selected charge storage device to program it. Approximately 10 volts are applied to the other access lines 620 in the block 512 and render the other charge storage devices associated with the selected pillar 504 conductive. The SGDs 630 in the block 512 that are biased to approximately 0 volts are not conductive, such that the pillars other than the selected pillar 504 are floating and have a potential that rises to approximately 8 volts due to the potential on the access lines 620 of approximately 10 volts to substantially prevent programming. The data line 533 coupled to the selected pillar 504 is between approximately 0 volts and approximately 1 volt to allow the selected charge storage device to be programmed and the other data lines 532 are biased to approximately 2.3 volts. The access lines 620, the SGDs 630, the SGSs 640 and the source gate 650 in the block 510 are at approximately 0 volts. The data lines 532 and 533 and the silicon well 610 are at the same potential for the blocks 510 and 512.

The source gate 650 in the block 512 is switched off to substantially reduce leakage of current to the n+ type diffusion region 528 and the member 524 and this can reduce program disturb activity during the programming. The voltage applied to the SGSs 640 and 670 can be higher than the approximately 3 volts, such as to reduce an electromagnetic field between the SGSs 640 and 670 and the access lines 620 and 622.

The selected charge storage device is erased when the voltages shown in Table 6 are applied to the semiconductor construction 500.

TABLE 6 Block 512 Block 510 Data lines 532, 533 ~20 V ~20 V Access lines 620, 622  ~0 V ~20 V SGDs 630, 660 ~20 V ~20 V SGSs 640, 670 ~20 V ~20 V Source gate 650 ~20 V ~20 V Member 524 ~20 V ~20 V Silicon Well 610 ~20 V ~20 V

Approximately 20 volts is applied to the silicon well 610 such that the potential on the pillars 504 rises to approximately 20 volts. The SGSs 640 and 670, the member 524, the source gate 650, the SGDs 630 and 660 and the data lines 532 and 533 are left floating and rise to approximately 20 volts from capacitive coupling with the pillars 504. Approximately 0 volts are applied to the access lines 620 and 622 in the block 512 to erase the charge storage devices associated with the pillar 504 above the SGS 670. The access lines 620 in the block 510 are left floating and rise to approximately 20 volts from capacitive coupling with the pillars 504.

FIG. 8 is a cross-sectional view of the semiconductor construction 200 along line 8-8 according to various embodiments of the invention. FIG. 8 illustrates four of the pillars 204 in the block 218 extending from the data line 233 to the p-type silicon well 310 and the tiers including the access lines 320 and 322, the SGDs 330, the SGSs 340 and the source gate 350. Silicon dioxide 810 is formed at edges of the SGDs 330. FIG. 8 illustrates charge storage devices 820 between the access lines 320 and 322 and the pillars 204. Each charge storage device 820 includes a polysilicon storage layer 830 separated from one of the pillars 204 by a tunnel dielectric 840 that can be silicon dioxide. The charge storage layer 830 is separated from the access line 320 or 322 by a blocking dielectric 850 that can include silicon dioxide, silicon nitride (Si₃N₄) and silicon dioxide (ONO).

FIG. 9 is a flow diagram of a method 900 according to various embodiments of the invention. In block 910, the method 900 starts. In block 920, strings are coupled to data lines. In block 930, the strings are coupled to a substrate. In block 940, some of the strings are substantially electrically isolated from the substrate. In block 950, the method 900 ends. Various embodiments may have more or fewer activities than those shown in FIG. 9. In some embodiments, the activities may be repeated, and/or performed in serial or parallel fashion. Some embodiments may comprise the same activities in a different order.

FIG. 10 is a diagram illustrating a system 1000 according to various embodiments of the invention. The system 1000 may include a processor 1010, a memory device 1020, a memory controller 1030, a graphic controller 1040, an input and output (I/O) controller 1050, a display 1052, a keyboard 1054, a pointing device 1056, and a peripheral device 1058. A bus 1060 couples all of these devices together. A clock generator 1070 is coupled to the bus 1060 to provide a clock signal to at least one of the devices of the system 1000 through the bus 1060. The clock generator 1070 may include an oscillator in a circuit board such as a motherboard. Two or more devices shown in system 1000 may be formed in a single integrated circuit chip. The memory device 1020 may comprise one or more of the block 100 of memory cells described herein and shown in the figures (e.g., see FIGS. 1A and 1B) according to various embodiments of the invention.

The memory device 1020 may comprise one or more of the semiconductor constructions 200, 500 and 800 described herein and shown in the figures according to various embodiments of the invention. The bus 1060 may be interconnect traces on a circuit board or may be one or more cables. The bus 1060 may couple the devices of the system 1000 by wireless means such as by electromagnetic radiations, for example, radio waves. The peripheral device 1058 coupled to the I/O controller 1050 may be a printer, an optical device such as a CD-ROM and a DVD reader and writer, a magnetic device reader and writer such as a floppy disk driver, or an audio device such as a microphone.

The system 1000 represented by FIG. 10 may include computers (e.g., desktops, laptops, hand-helds, servers, Web appliances, routers, etc.), wireless communication devices (e.g., cellular phones, cordless phones, pagers, personal digital assistants, etc.), computer-related peripherals (e.g., printers, scanners, monitors, etc.), entertainment devices (e.g., televisions, radios, stereos, tape and compact disc players, video cassette recorders, camcorders, digital cameras, MP3 (Motion Picture Experts Group, Audio Layer 3) players, video games, watches, etc.), and the like.

Charge storage devices in NAND memory devices can be subject to read disturb stress during read operations. The inventors have discovered that the challenges noted above, as well as others, can be addressed with, for example, a source gate device coupled to strings between one or more source select devices and a well in a substrate. Read disturb stress can be substantially reduced by turning off the source select devices in deselected strings during a read operation to substantially electrically isolate the deselected strings from the well in the substrate to substantially prevent conduction between the deselected strings and the well. A conductive member coupled to the substrate can reduce resistance to current flow in the well in the substrate.

Example structures and methods of fabricating semiconductor devices have been described. Although specific embodiments have been described, it will be evident that various modifications and changes may be made to these embodiments. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.

The Abstract of the Disclosure is provided to comply with 37 C.F.R. § 1.72(b), requiring an abstract that allows the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the claims. In addition, in the foregoing Detailed Description, it may be seen that various features are grouped together in a single embodiment for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as limiting the claims. Thus, the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separate embodiment. 

1. (canceled)
 2. A memory device, comprising: multiple vertical strings of memory cells, each string of memory cells comprising multiple memory cells associated with a respective semiconductor channel material, wherein the multiple vertical strings of memory cells each include first and second select transistors which each partially control conduction between a common source and the semiconductor channel material, wherein each of the first and second select transistors in the respective vertical strings of memory cells include respective control gates; wherein the control gates of the first select transistors of the multiple memory cell strings are coupled together to be controlled in common; and wherein the control gates of the second select transistors of a first portion of the multiple strings are coupled together to be controlled together, but controlled separately from the control gates of the second select transistors of a second portion of the multiple strings.
 3. The memory device of claim 2, wherein the multiple vertical strings of memory cells are the vertical strings of memory cells in a block of memory cells.
 4. The memory device of claim 3, wherein the block of memory cells includes multiple sub-blocks of memory cells, each sub-block including multiple vertical strings of memory cells.
 5. The memory device of claim 2, wherein the multiple vertical strings of charge storage memory cells further include respective drain select transistors, the drain select transistors having respective control gates, the drain select transistors controlling conduction to an individual data line of multiple data lines; wherein the control gates of the drain select transistors of the first portion of the multiple strings are coupled together to be controlled in common.
 6. The memory device of claim 2, wherein the control gates of the first select transistors of respective strings of memory cells at least partially surrounds the semiconductor channel material of the respective string of memory cells.
 7. The memory device of claim 6, wherein the control gates of the second select transistors of respective strings of memory cells at least partially surrounds the semiconductor channel material of the respective string of memory cells.
 8. The memory device of claim 2, wherein each of the second select gate of the respective string of memory cells is between multiple charge storage devices of the respective string of memory cells and the first select gate of the respective string.
 9. The memory device of claim 4, wherein a first sub-block comprises only strings of memory cells in a single column of the block.
 10. The memory device of claim 9, wherein a first sub-block comprises all strings of memory cells in a single column of the block.
 11. The memory device of claim 4, wherein each block of strings of memory cells comprises four sub-blocks of strings of memory cells.
 12. The memory device of claim 4, wherein the memory cells of respective vertical strings of memory cells are charge storage device memory cells in a string formed in a respective tier of multiple vertically arranged tiers, wherein multiple access lines form gates of multiple charge storage memory cells in the respective tier.
 13. The memory device of claim 12 wherein each respective access line forms gates of multiple memory cells formed in a respective tier and located in separate vertical strings of memory cells within the block.
 14. The memory device of claim 12, wherein the charge storage memory cells are floating gate memory cells.
 15. The memory device of claim 12, wherein the charge storage memory cells are charge trap memory cells.
 16. The memory device of claim 13, wherein each respective access line forms gates of memory cells in all respective vertical strings of memory cells within the block.
 17. A memory device, comprising: a block of multiple vertical strings of memory cells, each string of memory cells comprising multiple memory cells associated with a respective semiconductor channel material, wherein the multiple strings of memory cells each include a source gate transistor (SG) and a source gate select (SGS) transistor, which each partially control conduction between a source and the semiconductor channel material of the string; wherein gates of the source gate (SG) transistors of the multiple memory cell strings are coupled to an SG select line to be controlled in common; and wherein gates of the source gate select (SGS) transistors of a first portion of the multiple strings are coupled to a first SGS select line to be controlled together, and gates of the source gate select (SGS) transistors of a second portion of the multiple strings are coupled to a second SGS select line to be controlled together.
 18. The memory device of claim 17, wherein the block of multiple vertical strings of memory cells comprises multiple sub-blocks of vertical strings of memory cells, with each some block of vertical strings of memory cells having a respective portion of the multiple vertical strings of memory cells.
 19. The memory device of claim 18, wherein the memory cells of the multiple vertical strings of memory cells are floating gate flash memory cells.
 20. The memory device of claim 18, wherein the memory cells of the multiple strings of memory cells are charge trap flash memory cells.
 21. The memory device of claim 18, wherein the source select gate (SGS) transistors in each respective sub-block of the multiple sub-blocks of vertical strings of memory cells are coupled to a respective SGS select line for the sub-block to be controlled together. 